Related ScriptsProforma- Rechnung - the customers can print out a proforma bill for itself in her accountJanuary 27th 2012FreewareThe ea-Geier is an open-source tool written in PHP intended to handle accounting on a cash bases for Austrian companies (Buchhaltung zur Einnahmen-Ausgaben- Rechnung). With modular accounts code and a multi-lingual design, it is easily adjustable for other countries.The development.March 10th 2012FreewareEasyFFLib ist eine Klassenbibliothek welche den Umgang mit Ordnern und Dateien erleichtern soll.
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Paint.NET depends on Microsoft's.NET Framework 4.7.2, which is automatically installed if it isn't already on the system. Paint.NET will automatically run in 64-bit mode if possible. You must have a 64-bit capable CPU and an x64 edition of Windows. This download is licensed as freeware for the Windows (32-bit and 64-bit) operating system on a laptop or desktop PC from file organizer software without restrictions. SymMover 1.5.1510 is available to all software users as a free download for Windows 10 PCs but also without a hitch on Windows 7 and Windows 8.
US2A1 - Integrated photodiode of the floating substrate type- Google Patents US2A1 - Integrated photodiode of the floating substrate type- Google Patents Integrated photodiode of the floating substrate typeInfo Publication number US2A1 US2A1 US11/432,678 US43267806A USA1 US 2 A1 US2 A1 US 2A1 US 43267806 A US43267806 A US 43267806A US A1 US A1 US A1 Authority US United States Prior art keywords upper layer buried layer floating substrate layer integrated circuit Prior art date 2005-05-13 Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.) Granted Application number US11/432,678 Other versions Inventor Francois Roy Arnaud Tournier Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)STMicroelectronics SAOriginal Assignee STMicroelectronics SA Priority date (The priority date is an assumption and is not a legal conclusion.
Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.) 2005-05-13 Filing date 2006-05-10 Publication date 2006-05-13 Priority to FR0504836 priority Critical 2005-05-13 Priority to FR0504836 priority 2006-05-10 Application filed by STMicroelectronics SA filed Critical STMicroelectronics SA 2006-06-16 Assigned to STMICROELECTRONICS S.A. Reassignment STMICROELECTRONICS S.A. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). An integrated circuit includes at least one photodiode of the floating substrate type which is associated with a read transistor.
The photodiode is formed from a buried layer lying beneath the floating substrate and an upper layer lying on the floating substrate. The upper layer incorporates the source and drain regions of the read transistor.
The source and drain regions are produced on either side of the gate of the read transistor. An isolating trench is located alongside the source region and extends from the upper surface of the upper layer down to below the buried layer, so as to isolate the source region from said buried layer. Conventionally, photodiodes of the floating substrate type provide the isolation between the various pixels of an image sensor by producing a read transistor in which the gate is of circular type as opposed to rectangular type. This is because, to completely isolate the floating substrate, it is necessary to surround it with a semiconductor region of opposite type to it, while preventing the source and drain from being short-circuited. It is therefore imperative to use photodiodes having a gate with a circular structure, in which the buried layer of the photodiode is connected to the drain but the source is isolated from the buried layer by the gate of the read transistor that surrounds it. In accordance with an embodiment of the invention, an integrated circuit comprises a plurality of photodiodes, each photodiode of the floating substrate type comprising a buried layer lying beneath a floating substrate and an upper layer lying on the floating substrate.
A read transistor is associated with each photodiode and includes source and drain regions incorporated into the upper layer and produced on either side of a gate of the read transistor. A first isolating trench is located alongside said source region of each read transistor and extends from an upper surface of the upper layer down to below the buried layer, so as to isolate the source region from said buried layer. In accordance with another embodiment, an integrated circuit comprises a photodiode of the floating substrate type comprising a buried layer lying beneath a floating substrate and an upper layer lying on the floating substrate, the upper layer including a first and second portions. A read transistor is associated with the photodiode and includes source and drain regions incorporated into the first portion of the upper layer and produced on either side of a gate of the read transistor. A first trench isolation structure extends through the upper layer and into the floating substrate, the first trench isolation structure dividing the upper layer into the first and second portions. In accordance with another embodiment, an integrated circuit comprises a photodiode of the floating substrate type comprising a buried layer lying beneath a floating substrate and an upper layer lying on the floating substrate, the upper layer including a first and second portions. A read transistor is associated with the photodiode and includes source and drain regions incorporated into the first portion of the upper layer and produced on either side of a gate of the read transistor.
A first trench isolation structure extends through the upper layer and into the floating substrate, the first trench isolation structure dividing the upper layer into the first and second portions. A semiconductor contact region of a same conductivity type as the buried layer extends down to contact with the buried layer. A second trench isolation structure extends through the upper layer and into the floating substrate, the second trench isolation structure dividing the second portion of the upper layer from the semiconductor contact region.
In accordance with another embodiment, an integrated circuit comprises a photodiode of the floating substrate type comprising a buried layer lying beneath a floating substrate and an upper layer lying on the floating substrate, the upper layer including a first and second portions. A read transistor is associated with the photodiode and includes source and drain regions incorporated into the first portion of the upper layer and produced on either side of a gate of the read transistor.
A semiconductor contact region of a same conductivity type as the buried layer extends down to contact with the buried layer. A first trench isolation structure extends through the upper layer and floating substrate at least to an upper surface of the buried layer, the first trench isolation structure separating the second portion of the upper layer from the semiconductor contact region.BRIEF DESCRIPTION OF THE DRAWINGS. The various implantations may be carried out without using a mask other than protective masks for certain parts of the integrated circuit and a mask so that the floating substrate FSB is surrounded by a semiconductor layer of an opposite conductivity type.
This is because the successive implantations IMpdi are directly self-aligned with respect to the various trenches DTI 1, DTI 2, STI 1 and STI 2 which do not require protective masks since they are filled with oxide. Thus any uncertainty associated with the masking is eliminated. 13 shows another embodiment of the integrated circuit according to the invention. This embodiment no longer includes the two auxiliary isolating trenches STI 1 and STI 2, but does retain a contact region CR on the buried layer BL. To isolate the contact region CR from the upper layer 5 sufficiently to prevent the diffusion of dopants being able to take place during the various annealing operations of the fabrication process, the integrated circuit includes, between the contact region CR and the floating substrate FSB, another isolating trench MTI.
This isolating trench is preferably of the medium trench isolation type. This isolating trench MTI extends down to the buried layer BL so as to completely separate the floating substrate FSB from the contact region CR.
The integrated circuit as in claim 18 further including an over-doped pocket of a same conductivity type as the floating substrate located within the floating substrate underneath the gate of the read transistor and between the source and drain regions.
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